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NJU26040 Series
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NJU26040 Series Data Sheet
General Description
The NJU26040 Series a Digital Signal Processor with built-in OTP (One Time Programmable). By the DSP with built-in OTP, customization is possible from various sound technology. The NJU26040 Series is suitable for TV, mini-component, speakers system and other audio products. This DSP can constitute a small system by combining a CODEC.
Package
NJU26040V
FEATURES
* 24bit Fixed-point Digital Signal Processing * System Clock Frequency : Maximum 38MHz * Digital Audio Interface : 3 Input ports / 3Output ports * Digital Audio Format : I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs * Master / Slave Mode : In Master mode, MCK : 768/384/256fs * Serial Host Interface : I2C bus (Standard-mode/100kbps, First-mode/400kbps) : 4-Wire Serial bus (Clock, Enable, Input data, Output data) * Power Supply : 3.3 V * Input terminal : 5.0V Input tolerant * Package : SSOP32 ( Pb-Free )
Block Diagram
A D 1 /S D IN A D 2 /S S b S E R IA L A U D IO IN T E R F A C E BCKO PROGRAM CONTROL 2 4 -B IT x 2 4 -B IT M U L T IP L IE R ALU RESETb MCK CLKOUT CLK LRI T IM IN G GENERATOR A D D R E S S G E N E R A T IO N U N IT LRO SDO0 SDI [2 :0 ] SDO1 SDO2 BCKI S C L /S C K 2 4 b it F ix e d -p o in t D S P C o r e S E R IA L HOST IN T E R F A C E
S D A /S D O U T
DATA RAM
F IR M W A R E O T P /R A M
G P IO 3 G e n e r a l I/O IN T E R F A C E G P IO 2 G P IO 1 G P IO 0
Fig.1 NJU26040 Hardware Block Diagram
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Pin Configuration
VDD SDA / SDOUT SCL / SCK AD1 / SDIN AD2 / SSb RESETb VDD VDD VSS CLKOUT CLK SDI2 SDI1 SDI0 LRI BCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS TEST TEST GPIO0 GPIO1 GPIO2 GPIO3 / TEST VDD VSS TEST MCK SDO2 SDO1 SDO0 LRO BCKO
Fig. 2 Pin Configuration
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Pin Description
Table 1 Pin Description Pin No. Symbol 1, 7, 8, 25 VDD 2 3 4 5 6 9, 24, 32 10 11 12 13 14 15 16 17 18 19 20 21 22 23, 30, 31 26 27 28 29 Note : I IO OD I/O+ I/O SDA / SDOUT I/O Description
SCL / SCK AD1 / SDIN AD2 / SSb RESETb VSS CLKOUT CLK SDI2 SDI1 SDI0 LRI BCKI BCKO LRO SDO0 SDO1 SDO2 MCK TEST GPIO3/ TEST GPIO2 GPIO1 GPIO0 : Input : Input (Pull-down) : Output : Bi-directional (Open Drain) This pin requires a pull-up resistance. : Bi-directional (with Pull-up resistance) : Bi-directional (with Pull-down resistance)
Power Supply +3.3V / 4-Wire Serial Output I2C I/O This pin requires a pull-up resistance in both I2C bus and 4-Wire OD serial mode. 2 I I C Clock / Serial Clock I I2C Address / Serial Input I I2C Address / Serial Enable I Reset (RESETb='Low' : DSP Reset) GND O OSC Output I OSC Clock Input I Audio Data Input 2 I Audio Data Input 1 I Audio Data Input 0 I LR Clock Input I Bit Clock Input O Bit Clock Output O LR Clock Output O Audio Data Output 0 O Audio Data Output 1 O Audio Data Output 2 O Master Clock Output for A/D, D/A Ifor Test (connected to VSS) I/O + General Purpose IO 3 / for Test (Not connected : OPEN ) I/O - General Purpose IO 2 I/O - General Purpose IO 1 I/O - General Purpose IO 0
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Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings Parameter Symbol Supply Voltage In, OD I/O Pin Voltage * Out CLK CLKOUT Power Dissipation Operating Voltage Storage Temperature VDD Vx(IN),Vx(OD) Vx(I/O) Vx(OUT) Vx(CLK) Vx(CLKOUT)
( VSS=0V=GND, Ta=25C ) Rating Units
-0.3 to 3.8 -0.3 to 5.5 (VDD 3.0V) -0.3 to 3.8 (VDD < 3.0V) -0.3 to 3.8 -0.3 to 3.8 -0.3 to 3.8 -0.3 to 3.8
V
V
PD 500 mW TOPR -40 to 85 C -40 to 125 TSTR C * The LSI must be used inside of the "Absolute maximum ratings". Otherwise, a stress may cause permanent damage to the LSI. * Vx(IN) : 3, 4, 5, 6, 12,13,14,15,16, 23, 30, 31 pin * Vx(OD) : 2 pin * Vx(I/O) : 26, 27, 28, 29 pin * Vx(OUT) : 17, 18, 19, 20, 21, 22 pin * Vx(CLK) : 11 pin * Vx(CLKOUT) : 10 pin
Terminal equivalent circuit diagram
VDD RPU PAD RPD VSS Input, I/O (Input part) (With RPU: 26 pin ) (With RPD : 23, 27 to 31pin ) VDD PAD
Output Disable CLK CLKOUT
VDD
VSS CLK / CLKOUT (No.10, 11 pin)
VSS
Output, I/O ( Output part ) (No.2pin: Open Drain Output)
Fig.3 NJU26040 Terminal equivalent circuit diagram
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Electric Characteristics
Table 3 Electric Characteristics
Parameter Operating Voltage Operating Current High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Symbol VDD IDD VIH VIL VOH VOL IIN Leakage Current
*4
( VDD=3.3V, fOSC=36.864MHz, Ta=25C ) Test Condition VDD pin VDD=3.3V
*1
Min. 3.0 VDD x 0.7 0
Typ. 3.3 42 36.864 50
Max. 3.6 VDD
*2
Units V mA
VDD x 0.3 VDD VDD x 0.2 10 10 100 100 38 55
IOH= -1mA IOL= 1mA
*3
V
VDD x 0.8 0 -10
IIN(PU) II(PD)N
VIN = VSS to VDD
-100 -10 -
A
Input Transition Time Clock Frequency Clock Duty Cycle
*5
tr / tf fOSC rEC No.11pin (CLK) No.11pin (CLK)
*6
ns MHz %
20 45
*1 Current of operation is at the starting time. It is an actual measurement (reference value) in the room temperature in standard firmware in the default state. *2 Open-Drain input/output pins are +5.0V tolerant except GPIO0,GPIO1/GPIO2,GPIO3 and CLK input pin at supply voltage VDD = 3.3V. *3 Except No.2pin: SDA/SDOUT (Open-Drain). *4 I IN(PU) : 26pin, I IN(PD) : 27,28,29,30,31 pin *5 The tr / tf of No.2,3,4,5 pins are specified separately. Refer to the software specification. *6 Use it by the clock frequency united with the specification of firmware. Refer to the software specification. Usually, the sampling frequency of 768 Fs is supplied to CLK pin.
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1. Power Supply, Input/Output terminal, Clock, Reset 1.1 Power Supply
The NJU26040 Series has a power supply VDD. To setup good power supply condition, the decoupling capacitors should be implemented at the all power supply terminals.
1.2 Input/Output terminal
It restricts, when the input terminals (SCL/SCK, AD1/SDIN, AD2/SSb, RESETb, SDI2, SDI1, SDI0, LRI, BCKI pins) and bi-directional Open-drain terminal (SDA/SDOUT pin) of NJU26040 Series, and VDD are supplied on regular voltage (VDD=3.3V), and it becomes +5V Input tolerant.
1.3 Clock
The NJU26040 Series CLK pin requires the system clock that should be related to the sample frequency768 Fs. The clock frequency of 36.864MHz(48kHz x 768) should be supplied to the NJU26040. Refer to the software specification. (For example : Fs=48kHz CLK=36.864MHz )
Note : The clock frequency of 36.864MHz(48kHz x 768) should be supplied to the NJU26040. Out of 36.864MHz(48kHz x 768) in Master mode. The NJU26040 Series can't process the decoding correctly. Please consult with manufacture of crystal oscillator / ceramic resonator enough in use of these parts. NJRC would not take the responsibility on the external parts of clock generating.
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1.4 Reset
To initialize the NJU26040 Series, RESETb pin should be set Low level during some period. After some period of Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26040 Series. After the power supply and the oscillation of the NJU26040 Series becomes stable, RESETb pin must be kept Low-level more than tRESETb period. (Fig.4) If RESETb terminal is fixed "Low" level, SDA /SDOUT pin is Hi-Z state compulsorily. A Hi-Z state is continued until a Serial Host Interface (SHI) is decided. Therefore, communication by SHI cannot be performed until a setup of internal hardware is completed. After RESETb pin level goes to "High" (after reset release), a setup of the internal hardware of a Serial Host Interface completes NJU26040 Series within 25ms. Then, it will be in the state which can communicate. How to select a Serial Host Interface,I2C bus or 4-Wire serial bus. Refer to the software specification.
VDD
CLK
OSC unstable
OSC stable
tRESETb
RESETb
Set up a Host Interface within 25ms.
Fig.4 Reset Timing
Table 4 Reset Time Symbol tRESETb
Time 300s
Note : If supply of a clock is stopped or the NJU26040 is reset again, putting a normal clock into CLK terminal, the period RESETb terminal of tRESETb is kept "Low" level.(Table 4) Next, the NJU26040 is reset. Then redo from initial setting.
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2. Digital Audio Clock
Digital audio data needs to synchronize and transmit between digital audio systems. The NJU26040 Series - master mode / slave mode - both of the modes are supported. - In Master mode; Use the clock of BCKO and a LRO pin output clock for digital audio data transfer. - In Slave mode; The clock output from a master device is needed for the input terminal of BCKI and LRI.
2.1 Audio Clock
Three kinds of clocks are needed for digital audio data transfer. (1) LR clock (LRI, LRO) is needed by serial-data transmission. It is the same as the sampling frequency of a digital audio signal. (2) Bit clock (BCKI, BCKO) is needed by serial-data transmission. It becomes the multiple of LR clock. (3) Master clock (MCK) is needed by A/D, D/A converter, etc. It becomes the multiple of LR clock. It is not related to serial audio data transmission. Bit clock (BCKI, BCKO) of NJU26040 Series is supporting 32fs and 64fs of LR clock rate. (Table 5, 6, 7) Moreover, regardless of the master mode / slave mode of NJU26040 Series, MCK clock pin outputs the clock which carried out 256fs (1/3 x CLK) after NJU26040 reset release. "STOP", "Buffer output (768 fs = 1/1 x CLK)", and an output setup of a "384fs(1/2 x CLK)" are possible by control command.(Table 7) Refer to the software specification. Table 5 Sampling Frequency and BCK, MCK, clock (In Slave mode) Mode Clock Signal Multiple Frequency 32kHz 44.1kHz LRI 1fs 32kHz 44.1kHz DSP BCKI (32fs) 32fs 1.024MHz 1.4112MHz Slave BCKI (64fs) 64fs 2.048MHz 2.822MHz * In Slave mode : BCKO / LRO output data is same as input data of BCKI / LRI.
48kHz 48kHz 1.536MHz 3.072MHz
Table 6 Sampling Frequency and BCK, MCK, clock (In Master mode) CLK pin frequency Mode Clock Signal Multiple Frequency 24.576MHz 33.8688MHz 36.864MHz LRO 1fs 32kHz 44.1kHz 48kHz DSP BCKO (32fs) 32fs 1.024MHz 1.4112MHz 1.536MHz Master BCKO (64fs) 64fs 2.048MHz 2.822MHz 3.072MHz Table 7 Sampling Frequency and BCK, MCK, clock (In Master/Slave mode) CLK pin frequency Mode Clock Signal Multiple Frequency 24.576MHz 33.8688MHz 256fs (1/3 CLK) 8.192MHz 11.2896MHz DSP 384fs (1/2 CLK) 12.288MHz 16.9344MHz Master/ MCK 768fs (1/1 CLK) 24.576MHz 33.8688MHz Slave "STOP" Fixed "Low" level
36.864MHz 12.288MHz 18.432MHz 36.864MHz
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3. Digital Audio Interface 3.1 Digital Audio Data Format
The NJU26040 Series can use three kinds of formats hereafter as industry-standard digital audio data format. : MSB is put on the 2nd bit of LR clock change rate.(1 bit is delayed to left stuffing) (1) I2S (2) Left-justified : LR clock -- MSB is placed for changing. (3) Right-justified : LSB is placed just before LR clock change rate. The main differences among three kinds of formats are in the position relation between LR clock (LRI, LRO) and an audio data (SDI, SDO). - In every format: : a left channel is transmitted previously. - In Right/Left-justified : LR clock ='High' shows a left channel. : LR clock="Low" shows a left channel. - I2S - The Bit clock BCK (BCKI, BCKO) is used as a shift clock of transmission data. The number of clocks more than the number of sum total transmission bits of a L/R channel is needed at least. - One cycle of LR clock is one sample of a stereo audio data. The frequency of LR clock becomes equal to a sample rate (Fs). - The NJU26040 supports serial data format which includes 32(32fs) or 64(64fs) BCK clocks. This serial data format is applied to both MASTER and SLAVE mode.
3.2 Serial Audio Data Input/output
The NJU26040 Series audio interface includes 3 data input lines: SDI0, SDI1 and SDI2 (Table 8). 3 data output lines: SDO0, SDO1 and SDO2. (Table 9). Refer to software specification. Table 8 Serial Audio Input Pin Description Pin No. Symbol Description 14 SDI0 Audio Data Input 0 13 SDI1 Audio Data Input 1 12 SDI2 Audio Data Input 2 Table 9 Serial Audio Output Pin Description Pin No. Symbol Description 19 SDO0 Audio Data Output 0 20 SDO1 Audio Data Output 1 21 SDO2 Audio Data Output 2
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The NJU26040 Series can use three kinds of formats hereafter as industry-standard digital audio data format; (1) I2S (2) Left-Justified (3) Right-justified and 16 / 18 / 20 / 24bits data length. (Fig.5-1 to Fig5-12) An audio interface input and output data format become the same data format.
LRI, LRO BCKI, BCKO
M SB
Left Channel
Right Channel
LSB 32 Clocks
M SB 32 Clocks
LSB
SDI, SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-1 I2S Data Format 64fs, 24bit Data
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB
23
Left Channel
Right Channel
SDI, SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-2 Left-Justified Data Format 64fs, 24bit Data
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel
SDI, SDO 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-3 Right-Justified Data Format 64fs, 24bit Data
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel
SDI, SDO
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-4 I S Data Format 64fs, 20bit Data
LRI, LRO BCKI, BC KO
M SB LSB 32 Clocks M SB 32 Clocks LSB
19
2
Left Channel
Right Channel
SD SD I, O
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-5 Left-Justified Data Format 64fs, 20bit Data
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel
SD SDO 2 1 0 I,
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-6 Right-Justified Data Format 64fs, 20bit Data
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LRI, LRO BC BC KI, KO
M SB
Left Channel
Right Channel
LSB 32 Clocks
M SB 32 Clock s
LSB
SD SD I, O
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-7 I2S Data Format 64fs, 18bit Data
LRI, LRO BCKI, BCKO
M SB LSB 32 Clocks M SB 32 Clocks LSB
17
Left Channel
Right Channel
SDI, SDO
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-8 Left-Justified Data Format 64fs, 18bit Data
LRI, LRO BC BC KI, KO
M SB LSB 32 Clocks M SB 32 Clocks LSB Left Channel Right Channel
SD SD 2 1 0 I, O
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-9 Right-Justified Data Format 64fs, 18bit Data
LRI, LRO BCKI, BCKO
M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel
SDI, SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-10 I S Data Format 32fs, 16bit Data
LRI, LRO BCKI, BCKO
M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel
2
SDI, SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-11 Left-Justified Data Format 32fs, 16bit Data
LRI, LRO BCKI, BCKO
M SB LSB M SB 16 Clocks 16 Clocks LSB Left Channel Right Channel
SDI, SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fig.5-12 Right-Justified Data Format 32fs, 16bit Data
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3.3 Serial Audio Input Timing
Table 10 Serial Audio Input Timing Parameters Parameter Symbol Test Condition
BCKI Frequency * BCKI Period * Low Pulse Width High Pulse Width BCKI to LRI Time * LRI to BCKI Time * Data Setup Time Data Hold Time ** ** fBCKI tSIL tSIH tSLI tLSI tDS tDH
Min 75 75 40 40 15 15
( VDD=3.3V, Ta=25C ) Typ. Max Units
6.5 MHz ns ns ns ns ns
* It is the regulation in slave mode. ** It is the regulation to BCKI in slave mode and to BCKO in master mode.
LRI
tSIH tSIL tSLI tLSI
BCKI
tDS tDH
SDI
Fig.6 Serial Audio Input Timing
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Table 11 Serial Audio Output Timing Parameters Parameter Symbol Test Condition BCKO to LRO Time * Data Output Delay tSLO tDOD CL:LRO, BCKO, SDO=25pF
Min -15 -
( VDD=3.3V, Ta=25C ) Typ. Max Units
-
15 15
ns ns
* It is the regulation in Master mode.
LRO
tSLO
BCKO
tDOD
SDO
Fig.7 Serial Audio Input Timing
Table 12 Serial Audio Clock Timing (In slave mode) Parameter Symbol Test Condition Clock Output Delay CL:LRO, BCKO, tPDL (LRI --> LRO) SDO=25pF Clock Output Delay DSP Slave Mode tPDB (BCKI --> BCKO)
( VDD=3.3V, Ta=25C )
Min -
Typ. -
Max 15 15
Units ns ns
LRI
LRO
tPDL
O
BCKI
BCKO
tPDB
Fig.8 Serial Audio clock Timing (In slave mode)
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4. Serial Host Interface
The NJU26040 Series can be controlled via Serial Host Interface (SHI) using either of two serial bus formats: I2C bus or 4-Wire serial bus.(Table 13) How to select a Serial Host Interface, I2C bus or 4-Wire serial bus. Refer to the software specification. Table 13 Serial Host Interface Pin Description Symbol I2C bus Format Pin No. (I2C bus / Serial) Serial Data Input/Output 2 SDA / SDOUT * (Open Drain Input/Output) 3 SCL / SCK * Serial Clock 4 AD1 / SDIN * I2C bus address Bit1 5 AD2 / SSb * I2C bus address Bit2
4-Wire Serial bus Format Serial Data Output (Open-Drain Output) Serial Clock Serial Data Input Serial enable
Note : SDA /SDOUT pin is a bi-directional open drain. This pin requires a pull-up resistance in both I2C bus and 4-Wire serial mode. * When the power supply (VDD= +3.3V) is supplied to NJU26040, these pins become +5.0V Input tolerant.
4.1 I2C bus
When the NJU26040 Series is configured for I2C bus communication during the Reset initialization sequence. I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. (Table 14) This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26040. An address can be arbitrarily set up by the AD1 and AD2 pins. The I2C address of AD1/AD2 is decided by connection of AD1/AD2 pins. The I2C address should be the same level of AD1/AD2 pins. The real I2C address is described in the software specification. Both "Standard-Mode (100kbps)" and "Fast-Mode (400kbps)" data transfer rate are supported. Table 14 I2C bus SLAVE Address
bit7 0 0 0 0 bit6 0 0 0 0 *1 bit5 1 1 1 1 bit4 1 1 1 1 bit3 1 1 1 1 bit2 *2 0 0 1 1
AD2
bit1 *2 0 1 0 1
AD1
R/W bit0 R/W
Start bit
Slave Address ( 7bit )
R/W bit
ACK
*1 : Refer to the software specification. *2 : SLAVE address is 0 when AD1/AD2 is "Low". SLAVE address is 1 when AD1/AD2 is "High".
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Table 15 I2C bus Interface Timing Parameters
Parameter SCL Clock Frequency Start Condition Hold Time SCL "Low" Duration SCL "High" Duration Start Condition Setup Time Data Hole Time *1 Data Setup Time Rising Time Falling Time Stop Condition Setup Time Bus Release Time *2 Symbol fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tBUF
( VDD=3.3V, fOSC=36.864MHz, Ta=25C )
Min 0 0.6 1.3 0.6 0.6 0 250 0.6 1.3
Max 400 0.9 1000 300 -
Units kHz s s s s s ns ns ns s s
SDA tBUF tR tF tHD:STA
SCL
tHD:STA t LOW P S
tHD:DAT
tHIGH
tSU:DAT Sr
tSU:STA
tSU:STO P
Fig.9 I2C bus Timing
Note : *1 tHD:DAT: Keep data 100ns hold time to avoid indefinite state by SCL falling edge. *2 This item shows the interface specification. The interval of a continuous command is specified separately.
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4.2 4-Wire Serial Interface
When the NJU26040 Series is configured for 4-Wire Serial bus communication during the reset initialization sequence. 4-Wire Serial interface communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low (SSb = 0). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb.(Table16, Fig.10) Table 16 4-Wire Serial Interface Timing Parameters ( VDD=3.3V, fOSC=36.864MHz ,SDOUT=25pF, Ta=25C )
Parameter Input Data Rising Time Input Data Falling Time Serial Clock Rising Time Serial Clock Falling Time Serial Strobe Rising Time Serial Strobe Falling Time Serial Clock High Duration Serial Clock Low Duration Serial Clock Period Serial Strobe Setup Time Serial Strobe Hold Time Serial Strobe Low Duration *1 Serial Strobe High Duration *1 Input Data Setup Time Input Data Hold Time Output Data Hold Time Output Data Turn off Time (Hi-Z) Symbol tMSDr tMSDf tMSCr tMSCf tMSSr tMSSf tMSCa tMSCn tMSCc tMSSs tMSSh tMSSa tMSSn tMSDis tMSDih tMSDoh tMSDov Min. 0.5 0.5 1.0 0.5 0.5 0.1 0.1 Typ. 8.5 1.0 Max. 100 100 100 100 100 100 0.25 0.25 Units ns ns ns ns ns ns s s s s s s s s s s s
tMSDr, tMSDf SDIN B7 tMSDis tMSCr SCK tMSCa SDOUT Hi-Z tMSDoh tMSSf SSb tMSSa Fig.10 4-Wire Serial Interface Timing Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side. *1 : It is not a continuous command interval. - 16 Ver.2006-09-13
B6 tMSDih tMSCn tMSCc
B5
B4
B3
B2
B1
B0
tMSCf tMSDoh B6 B5 B4 B3 B2 B1 B0
unstable
B7 tMSSs
Hi-Z tMSDov
tMSCa tMSSr
tMSSn
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5. General Purpose I/O (GPIO) Ports
NJU26040 Series has four general purpose Input/Output (GPIO) ports. - GPIO0, GPIO1, GPIO2 : Bi-directional (with Pull-down resistance) - GPIO3 : Bi-directional (with Pull-Up resistance)
Note :
Until firmware starts, please set GPIO3/TEST1 pin should be "High" level after NJU26040 reset release. In case of GPIO3/TEST1 pin is "Low" level. The NJU26040 can't operate. GPIO3/TEST1 pin is must be not connected (OPEN).
6. Package Dimensions
11.0
( SSOP32, Pb-Free )
+0.3 -0.1
0 ~ 10 17
32
5.6 0.2
7.6 0.3
1 0.75 MAX.
0.65
16 0.15 +0.10 -0.05
+0.10 -0.05
0.1 0.22 0.1
1.15 0.1
0.1
M
0.1
Unit : mm
1
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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0.5 0.2
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